module DDS_DIV_ADDR
(
	CLK,
	RSTn,
	DIV_PAR,
	OUT
)

	input CLK;
	input Rstn;
	input [15:0]DIV_PAR;
	output OUT;
	
	reg clkout;
	reg [15:0]cnt;
	
	always @ (posedge CLK or negedge RSTn)
	begin
		if(!RSTn)
		begin
			clkout <= 0;
			cnt	 <= 16'd0;
		end
		else if (cnt == DIV_PAR)
		begin
			clkout <= ~clkout;
		end
		else
		begin
			cnt <= cnt + 1'b1;
		end
	end
	